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iC-NQC TSSOP20-Sample

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Price per Sample Box: $72.50 (Sample Box/5 pcs) ($14.50 each)
RoHS Status: Yes

Quantity in Stock:11

Description Features
iC-NQC is a monolithic A/D converter which, by applying a count-safe vector follower principle, converts sine/cosine sensor signals with a selectable resolution
and hysteresis into angle position data.

This absolute value is output via a bidirectional, synchronous-serial I/O interface in BiSS C protocol and trails a master clock rate of up to 10 Mbit/s. Alternatively, this value can be output so that it is compatible with SSI in Gray or binary code, with or without error bits. The device also supports double transmission in SSI ring mode.

Signal periods are logged quickly by a 24-bit period counter that can supplement the output data with an upstream multiturn position value.

At the same time any changes in angle are converted into incremental A QUAD B signals. Here, the minimum transition distance can be stipulated and adapted to suit the system on hand (cable length, external counter). A synchronized zero index Z is generated if enabled by PZERO and NZERO.

The front-end amplifiers are configured as instrumentation amplifiers, permitting sensor bridges to be directly connected without the need for external resistors. Various programmable D/A converters are available for the conditioning of sine/cosine sensor signals with regard to offset, amplitude ratio and phase errors (offset compensation by 8-bit DAC, gain ratio by 5-bit DAC, phase compensation by 6-bit DAC).

The front-end gain can be set in stages graded to suit all common complementary sensor signals from approximately 20 mVpp to 1.5 Vpp and also noncomplementary sensor signals from 40 mVpp to 3 Vpp respectively.

The device can be configured using two bidirectional interfaces, the EEPROM interface from a serial EEPROM with I2C interface, or the I/O interface in BiSS C protocol. Free storage space on the EEPROM can be accessed via BiSS for the storage of additional data.

After a low voltage reset, iC-NQC reads in the configuration data including the check sum (CRC) from the EEPROM and repeats the process if a CRC error is detected.

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