iC-MFL QFN24 Sample
Product Code: iC-MFL SAMPLE
Our Price: $36.25
Description
iC-MFL / iC-MFLT is a monolithically integrated, 8/12-channel level adjustment device which drives N-channel FETs. The internal circuit blocks have been designed in such a way that with single errors, such as open pins (VCC, GND, GNDR) or the short-circuiting of two outputs, iC-MFL’s output stages switch to a predefined, safe low state. Externally connected N-channel FET are thus shut down safely in the event of a single error. The inputs of the eight/twelve channels consist of a Schmitt trigger with a pull-down current source and are compatible with TTL and CMOS levels (1.8 to 5 V). The eight/twelve channels have a current-limited push-pull output stage and a pull-down resistor at the output. The output stages supply an output signal of 5 V and are enabled by a high signal at pin EN. Fur thermore, all stages can handle surge voltage pulses (max. 18 V, pulse width < 100 ms, max. 2 % duty cycle) at the output. iC-MFL monitors the supply voltage at VCC pin and the voltages at the two ground pins GND and GNDR. The pins GND and GNDR must be connected together externally in order to guarantee the safe low state of the output stages in the event of error. Should the supply voltage at VCC undershoot a predefined threshold, the voltage monitor causes the outputs to be actively tied to GND via the low-side transistors. If the supply voltage ceases to be applied to VCC, the outputs are tied to GNDR by pull-down resistors. If the connection between the ground potential and the GND pin is disrupted, the highside and low-side transistors of the output stages are shut down and the outputs tied to GNDR via the pull-down resistors. If on the other hand the connection between ground potential and the GNDR pin is disrupted, only the output stage highside transistors are shut down; the outputs are then actively tied to GND via the low-side transistors. Open inputs IN1...8/12 and EN are actively tied to GND by pull-down currents. The pull-down currents have two stages in order to limit power dissipation with enhanced noise immunity. When two outputs of different logic states are short circuited, the driving capability of the lowside driver predominates, keeping the connected N-channel FETs in a safe shutdown state. The device is protected against destruction by ESD.
Features